Package Offering
From Leadframe to Wafer Level — A Full Spectrum of Packaging Solutions
2026 Package Calendar
Versatile Packaging Options Tailored for Performance
Our turnkey services include Package Development, Wafer Probing, Wafer Bumping/WLCSP, Assembly Packaging, Final Electrical Testing, Reliability Testing & Failure Analysis, Warehousing & Drop Shipment. And with our real-time WIP systems and drop shipping to OEM’s, Unisem offers its customers everything needed for time-to-market wins.
Unisem offers a broad range of standard and custom Leadframe and Laminate packages with pin counts ranging from 3 to 484+. Also offered are WLCSPs or Wafer-Level Chip-Scale Packages which is a low cost solution that enables direct connectivity at the substrate or board level.
We Offer Full Turnkey Solution
Modelling - 2012
Siyantika Glory
Hatha yoga built on a harmonious balance between body strength and softness
Modelling - 2012
Siyantika Glory
Hatha yoga built on a harmonious balance between body strength and softness
Modelling - 2012
Siyantika Glory
Hatha yoga built on a harmonious balance between body strength and softness
Modelling - 2012
Siyantika Glory
Hatha yoga built on a harmonious balance between body strength and softness
Modelling - 2012
Siyantika Glory
Hatha yoga built on a harmonious balance between body strength and softness
Modelling - 2012
Siyantika Glory
Hatha yoga built on a harmonious balance between body strength and softness
Modelling - 2012
Siyantika Glory
Hatha yoga built on a harmonious balance between body strength and softness
Unisem’s Full-Spectrum
Package Portfolio
Delivering Proven, Scalable, and Next-Gen Semiconductor Packaging Technologies
Laminate Packages
Leaded Packages
Leadless Packages
MEMS and Sensor
WLCSP
Laminate Packages
Greater flexibility in design, better of electrical insulation properties, laminate packages allow more complex electrical routing and various integration for advance application.
Unisem has vast experience with laminate package assembly and manufacturing. In fact, we’ve developed several in-house manufacturing capabilities that give us the flexibility needed to for quick design and manufacture of laminate products. So any manufacturing hurdles are quickly cleared, and any specialized needs are soundly addressed by our competent design and manufacturing team. The result? Optimized cost and yield for a variety of package designs
Core Offering
Tailored Solutions for Complex Demands
Laminate Technology Advantages: Enhanced electrical insulation, flexible routing, and advanced integration capabilities to power high-performance applications.
01
LGA/FLGA
– Land Grid Array / Fine-pitch Land Grid Array
– Serving as foundation for various packaging solutions which require enhance thermal and high electrical performance
– Reduce package footprint with higher I/O pin count designed for markets requiring miniaturization
02
BGA
– Ball Grid Array.
– Unisem offering wide range of BGA packages up to 25x25mm, integrate with different configurations (Wire bond, Flip Chip and SMT).
– BT substrate BGA features with standard/fine solder ball pitch.
– Build of Materials comply with halogen free, lead-free, REACH and RoHS regulations.
03
SiP / Module in Laminate
– Unisem’s SIP (System-In-Package) technology enhances functionality and integration in laminate packages.
– Ideal for wireless and other applications requiring system integration in a single package format.
– Supports multichip configurations, including combinations with passive components.
– Provides flexibility for communication between chiplets within the package.
04
Stacked Die
– Unisem’s offers 2 or more die stacking in a pyramid form, or same die size stack resulting in fewer package count and smaller footprint.
– Beside die-die stack, Unisem also experience in different stack configurations like:
– Stack Die on Inductor
– WB Die Stack on Flip Chip
– This near to chip-scale option is assembled using standard laminate (LGA/BGA) package, and is also available in leadframe / MIS platform.
– Wafer thinning, overhang wire bond technology and spacers are used between stacked die. Die to die bonding can also enhance the thermal and electrical performance.
05
EMI Shielding
– EMI (Electromagnetic Interference) shielding.
– Proper shielding is critical for ensuring reliable signal and data transfer in today’s communication systems and wireless devices.
– Unisem offers technology on creating isolation barrier to the package that prevent leakage of strong electromagnetic fields that can interfere with sensitive device and signal.
– Unisem has qualified shielding material layer, Ti-Cu-Ti on various laminate and MIS packages.
Leaded Packages
High-Yield, Cost-Efficient Leadframe Packaging
Unisem delivers industry-leading expertise in leadframe package assembly, combining process innovation with proven manufacturing technologies to drive higher yields and lower costs. Our comprehensive portfolio supports a wide range of consumer, communications, computing, and automotive applications.
Unisem Leadframe Package Portfolio:
01
SOIC
– Small Outline Integrated Circuit designed for footprint reduction requirement, and facilitates better heat dissipation increasing thermal performance with exposes paddle design.
– Good option for application where debugging and manual soldering needs.
– Available in 8 and 16 lead counts with 150mils body width.
– Offering in various configuration,
• Wire bond
• Flip chip
• Stack die
• Exposed paddle
• Chip on lead
02
QSOP
– Quarter-Size Outline Package, a more compact version of standard SOIC, featuring a compressed body and finer lead pitch for space constrained design.
– Available in 16 lead counts with 150mils body width.
03
TSSOP
– Thin Shrink Small Outline Package
– A thin (0.9mm) profile, fine pitch solution optimized for high performance ICs commonly used in analog, RF, logic, memory and optoelectronics application.
– Available in 14, 16, 20, 24 and 28 lead counts.
– Offering in various configuration,
• Wire bond
• Stack die
• Exposed paddle
04
SOT23/TSOT
– The most common Small Outline Transistor family are SOT23 variations.
– A small footprint, compact discrete SMT transistors available in 3, 5, 6 lead counts with package size 1.30mm.
– Offering SOT23 in below configuration,
• Wire bond
• Flip Chip
• Chip on Leads
– Unisem also manufacturing the nearly identical Thin Small Outline Transistor (TSOT) package, where a lower package height is crucial.
– TSOT available in 5 and 6 lead counts with package size 1.60mm
05
SC70
– Another common Small Outline Transistor, SC70 a much smaller footprint discrete than SOT23.
– Available in 3, 4, 5, 6 lead counts, wire bond configuration.
06
SOT563/SOT583
– 6 leads Small Outline Transistor and 8 leads Small Outline Transistor, compact small size with best light load efficiency, excellent thermal capability.
– Available in Flip Chip configuration.
Leadless Packages
Unisem: Pioneering Ultra-Compact Excellence for Next-Gen Electronics
Unisem’s leadless leadframe packages, such as SLP (Small Leadless Package) and MIS (Molded Interconnect Substrate), support product miniaturization with their smaller routing area, thinner profiles, and thermally enhanced designs. These packages are ideal solutions for applications in telecommunications and consumer electronics, including microcontrollers, power management ICs, and sensors. Additionally, various configurations—such as Stack Die, MCM, and SiP—can be applied to leadless leadframe packages, enhancing functionality and enabling efficient system integration within a single package format.
Unleash the Power of Miniaturization
01
SLP
– Smaller form and fit, shorter routing connection offers more compact footprint with excellent thermal performance.
– Unisem’s leadless leadframe packages such as SLP (Small Leadless Package) and MIS (Molded Interconnect Substrate) are one of the attractive solution which are ideal for hand held portable communications application where small, high-performance packages are required.
02
MIS
– Unisem uses MIS (Molded Interconnect Substrate) platform to create thin profile package of 0.33mm or lower. It is available in thicker profile as well.
– MIS uses build-up technology that enable it to achieve similar ultra fine-line / space capability which are comparable to conventional BT substrate and more cost effective.
– Its pre-molded structure with one or more layer allows high I/O density, complex interconnect Cu routing capability in a small form factor fits demands for devices requiring high performance solution with low noise or high frequency.
– It can cater various configuration such as wire bonding, flip chip, and SiP version.
03
SiP in SLP / MIS
– A relatively cost-effective packaging solution with SiP in SLP and MIS where it gives great thermal management with enhanced functionality and package performance.
– Experienced in Side-by-Side Placement, Stack Structure, Au / PdCu Wire Bond, SMT and flip chip bonding.
04
Wettable Flank
– Wettable flank enables side wall solder wetting during board mounting, and allow visible solder joint inspection from sides of the package. This allows customers to use standard AOI equipment to determine if a unit is mounted to the PCB boards adequately.
– Unisem started to offer QFN with Wettable Flank (WF) capability since year 2015 specifically to align with Automotive market requirement.
MEMS and Sensor
Specialized MEMS Packaging with Scalable Volume Capability
Micro-Electromechanical System (MEMS) is a miniature and lightweight version of machinery that integrates mechanical and electrical components. Durable, reliable, high in sensitivity, and offering lower cost and power consumption, MEMS technology is a favorable option for sensors compared to other technologies. Unisem has developed packaging solutions for many MEMS applications, including microphones for the mobile market, pressure sensors for automotive, and accelerometers for consumer and other markets. Unisem has the experience in both the design and manufacturing of the specialized packaging required for each unique MEMS design. High-volume MEMS packaging is available at Unisem factories.
01
LGA-FL
– Land Grid Array-Formed Lid Package.
– Laminate based cavity package cover by formed metal lid for consumer pressure sensor, gas sensor and microphones, where EMI shielding and high resistance to application pressure are required.
– Able to accommodates various backend process configuration,
• SMT for passives components
• Stack die / Multi die
• Wire bond / Flip chip
• Top / Bottom Port
• Glob top
02
LGA/QFN-MC
– Land Grid Array / Quad Flat No-lead – Molded Cavity Package.
– Utilizing Film Assisted Molding (FAM) technology to create the molded structure require by sensor aiming for higher absolute reliability performance over time.
– Option to have flat metal lid adhere on top of molded cavity which helps block electromagnetic interference for sensitive MEMS devices.
– Process configuration option,
• SMT for passives components
• Stack die / Multi die
• Wire bond / Flip chip
• Mold with customize design cavity
• Metal lid attach with or without port
• Full die coating / Glob top
03
LGA-ML
– Land Grid Array / Quad Flat No-lead – Molded Lid Package.
– A cavity MEMS package cover by LCP molded lid.
– The LCP lid can be customized to fit complex internal and external lid shape requirement than metal lid doesn’t have.
– Package options applicable,
• SMT / Silicon passives
• Stack die / Multi die
• Wire bond / Flip chip
• Top / Bottom port
• Internal / External chimney
• Single / dual cavity
• Glob top
04
SOIC
– MEMS in Small Outline Package where where the package has long history of reliability, and easy solder joint inspection at 2nd level assembly where the application suit in Automotive inertial sensors, accelerometer, and gyroscope.
– Package options applicable,
• Stack die / Multi die
• Wire bond / Flip chip
WLCSP
Wafer Level Packaging
Unisem provides a comprehensive Wafer Level Chip Scale Package (CSP) solution that enables direct connectivity at the substrate or board level, offering both cost efficiency and high performance. Our state-of-the-art facilities are equipped with laser marking, laser grooving, advanced 2D/3D wafer inspection, and high-speed die sorting, allowing us to deliver a full turnkey service—from wafer bumping and packaging to probing and complete wafer map integration. We support die sizes ranging from 0.2 sq.mm to 36 sq.mm, ensuring precision and reliability across various applications. Unisem is capable of handling both 8” and 12” wafers. Additionally, we offer Wafer Back Side Protection (BSP), a process that applies backside lamination after back grinding to reduce die chip-out during sawing and to provide a protective layer against mechanical im
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